root/kernel/virtio.h

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   1 //
   2 // virtio device definitions.
   3 // for both the mmio interface, and virtio descriptors.
   4 // only tested with qemu.
   5 //
   6 // the virtio spec:
   7 // https://docs.oasis-open.org/virtio/virtio/v1.1/virtio-v1.1.pdf
   8 //
   9 
  10 // virtio mmio control registers, mapped starting at 0x10001000.
  11 // from qemu virtio_mmio.h
  12 #define VIRTIO_MMIO_MAGIC_VALUE         0x000 // 0x74726976
  13 #define VIRTIO_MMIO_VERSION             0x004 // version; should be 2
  14 #define VIRTIO_MMIO_DEVICE_ID           0x008 // device type; 1 is net, 2 is disk
  15 #define VIRTIO_MMIO_VENDOR_ID           0x00c // 0x554d4551
  16 #define VIRTIO_MMIO_DEVICE_FEATURES     0x010
  17 #define VIRTIO_MMIO_DRIVER_FEATURES     0x020
  18 #define VIRTIO_MMIO_QUEUE_SEL           0x030 // select queue, write-only
  19 #define VIRTIO_MMIO_QUEUE_NUM_MAX       0x034 // max size of current queue, read-only
  20 #define VIRTIO_MMIO_QUEUE_NUM           0x038 // size of current queue, write-only
  21 #define VIRTIO_MMIO_QUEUE_READY         0x044 // ready bit
  22 #define VIRTIO_MMIO_QUEUE_NOTIFY        0x050 // write-only
  23 #define VIRTIO_MMIO_INTERRUPT_STATUS    0x060 // read-only
  24 #define VIRTIO_MMIO_INTERRUPT_ACK       0x064 // write-only
  25 #define VIRTIO_MMIO_STATUS              0x070 // read/write
  26 #define VIRTIO_MMIO_QUEUE_DESC_LOW      0x080 // physical address for descriptor table, write-only
  27 #define VIRTIO_MMIO_QUEUE_DESC_HIGH     0x084
  28 #define VIRTIO_MMIO_DRIVER_DESC_LOW     0x090 // physical address for available ring, write-only
  29 #define VIRTIO_MMIO_DRIVER_DESC_HIGH    0x094
  30 #define VIRTIO_MMIO_DEVICE_DESC_LOW     0x0a0 // physical address for used ring, write-only
  31 #define VIRTIO_MMIO_DEVICE_DESC_HIGH    0x0a4
  32 
  33 // status register bits, from qemu virtio_config.h
  34 #define VIRTIO_CONFIG_S_ACKNOWLEDGE     1
  35 #define VIRTIO_CONFIG_S_DRIVER          2
  36 #define VIRTIO_CONFIG_S_DRIVER_OK       4
  37 #define VIRTIO_CONFIG_S_FEATURES_OK     8
  38 
  39 // device feature bits
  40 #define VIRTIO_BLK_F_RO              5  /* Disk is read-only */
  41 #define VIRTIO_BLK_F_SCSI            7  /* Supports scsi command passthru */
  42 #define VIRTIO_BLK_F_CONFIG_WCE     11  /* Writeback mode available in config */
  43 #define VIRTIO_BLK_F_MQ             12  /* support more than one vq */
  44 #define VIRTIO_F_ANY_LAYOUT         27
  45 #define VIRTIO_RING_F_INDIRECT_DESC 28
  46 #define VIRTIO_RING_F_EVENT_IDX     29
  47 
  48 // this many virtio descriptors.
  49 // must be a power of two.
  50 #define NUM 8
  51 
  52 // a single descriptor, from the spec.
  53 struct virtq_desc {
  54   uint64 addr;
  55   uint32 len;
  56   uint16 flags;
  57   uint16 next;
  58 };
  59 #define VRING_DESC_F_NEXT  1 // chained with another descriptor
  60 #define VRING_DESC_F_WRITE 2 // device writes (vs read)
  61 
  62 // the (entire) avail ring, from the spec.
  63 struct virtq_avail {
  64   uint16 flags; // always zero
  65   uint16 idx;   // driver will write ring[idx] next
  66   uint16 ring[NUM]; // descriptor numbers of chain heads
  67   uint16 unused;
  68 };
  69 
  70 // one entry in the "used" ring, with which the
  71 // device tells the driver about completed requests.
  72 struct virtq_used_elem {
  73   uint32 id;   // index of start of completed descriptor chain
  74   uint32 len;
  75 };
  76 
  77 struct virtq_used {
  78   uint16 flags; // always zero
  79   uint16 idx;   // device increments when it adds a ring[] entry
  80   struct virtq_used_elem ring[NUM];
  81 };
  82 
  83 // these are specific to virtio block devices, e.g. disks,
  84 // described in Section 5.2 of the spec.
  85 
  86 #define VIRTIO_BLK_T_IN  0 // read the disk
  87 #define VIRTIO_BLK_T_OUT 1 // write the disk
  88 
  89 // the format of the first descriptor in a disk request.
  90 // to be followed by two more descriptors containing
  91 // the block, and a one-byte status.
  92 struct virtio_blk_req {
  93   uint32 type; // VIRTIO_BLK_T_IN or ..._OUT
  94   uint32 reserved;
  95   uint64 sector;
  96 };

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