1 // Physical memory layout 2 3 // qemu -machine virt is set up like this, 4 // based on qemu's hw/riscv/virt.c: 5 // 6 // 00001000 -- boot ROM, provided by qemu 7 // 02000000 -- CLINT 8 // 0C000000 -- PLIC 9 // 10000000 -- uart0 10 // 10001000 -- virtio disk 11 // 80000000 -- boot ROM jumps here in machine mode 12 // -kernel loads the kernel here 13 // unused RAM after 80000000. 14 15 // the kernel uses physical memory thus: 16 // 80000000 -- entry.S, then kernel text and data 17 // end -- start of kernel page allocation area 18 // PHYSTOP -- end RAM used by the kernel 19 20 // qemu puts UART registers here in physical memory. 21 #define UART0 0x10000000L 22 #define UART0_IRQ 10 23 24 // virtio mmio interface 25 #define VIRTIO0 0x10001000 26 #define VIRTIO0_IRQ 1 27 28 // qemu puts platform-level interrupt controller (PLIC) here. 29 #define PLIC 0x0c000000L 30 #define PLIC_PRIORITY (PLIC + 0x0) 31 #define PLIC_PENDING (PLIC + 0x1000) 32 #define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) 33 #define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) 34 #define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) 35 36 // the kernel expects there to be RAM 37 // for use by the kernel and user pages 38 // from physical address 0x80000000 to PHYSTOP. 39 #define KERNBASE 0x80000000L 40 #define PHYSTOP (KERNBASE + 128*1024*1024) 41 42 // map the trampoline page to the highest address, 43 // in both user and kernel space. 44 #define TRAMPOLINE (MAXVA - PGSIZE) 45 46 // map kernel stacks beneath the trampoline, 47 // each surrounded by invalid guard pages. 48 #define KSTACK(p) (TRAMPOLINE - ((p)+1)* 2*PGSIZE) 49 50 // User memory layout. 51 // Address zero first: 52 // text 53 // original data and bss 54 // fixed-size stack 55 // expandable heap 56 // ... 57 // TRAPFRAME (p->trapframe, used by the trampoline) 58 // TRAMPOLINE (the same page as in the kernel) 59 #define TRAPFRAME (TRAMPOLINE - PGSIZE)