root/kernel/kernelvec.S

   1         #
   2         # interrupts and exceptions while in supervisor
   3         # mode come here.
   4         #
   5         # the current stack is a kernel stack.
   6         # push all registers, call kerneltrap().
   7         # when kerneltrap() returns, restore registers, return.
   8         #
   9 .globl kerneltrap
  10 .globl kernelvec
  11 .align 4
  12 kernelvec:
  13         # make room to save registers.
  14         addi sp, sp, -256
  15 
  16         # save the registers.
  17         sd ra, 0(sp)
  18         sd sp, 8(sp)
  19         sd gp, 16(sp)
  20         sd tp, 24(sp)
  21         sd t0, 32(sp)
  22         sd t1, 40(sp)
  23         sd t2, 48(sp)
  24         sd s0, 56(sp)
  25         sd s1, 64(sp)
  26         sd a0, 72(sp)
  27         sd a1, 80(sp)
  28         sd a2, 88(sp)
  29         sd a3, 96(sp)
  30         sd a4, 104(sp)
  31         sd a5, 112(sp)
  32         sd a6, 120(sp)
  33         sd a7, 128(sp)
  34         sd s2, 136(sp)
  35         sd s3, 144(sp)
  36         sd s4, 152(sp)
  37         sd s5, 160(sp)
  38         sd s6, 168(sp)
  39         sd s7, 176(sp)
  40         sd s8, 184(sp)
  41         sd s9, 192(sp)
  42         sd s10, 200(sp)
  43         sd s11, 208(sp)
  44         sd t3, 216(sp)
  45         sd t4, 224(sp)
  46         sd t5, 232(sp)
  47         sd t6, 240(sp)
  48 
  49         # call the C trap handler in trap.c
  50         call kerneltrap
  51 
  52         # restore registers.
  53         ld ra, 0(sp)
  54         ld sp, 8(sp)
  55         ld gp, 16(sp)
  56         # not tp (contains hartid), in case we moved CPUs
  57         ld t0, 32(sp)
  58         ld t1, 40(sp)
  59         ld t2, 48(sp)
  60         ld s0, 56(sp)
  61         ld s1, 64(sp)
  62         ld a0, 72(sp)
  63         ld a1, 80(sp)
  64         ld a2, 88(sp)
  65         ld a3, 96(sp)
  66         ld a4, 104(sp)
  67         ld a5, 112(sp)
  68         ld a6, 120(sp)
  69         ld a7, 128(sp)
  70         ld s2, 136(sp)
  71         ld s3, 144(sp)
  72         ld s4, 152(sp)
  73         ld s5, 160(sp)
  74         ld s6, 168(sp)
  75         ld s7, 176(sp)
  76         ld s8, 184(sp)
  77         ld s9, 192(sp)
  78         ld s10, 200(sp)
  79         ld s11, 208(sp)
  80         ld t3, 216(sp)
  81         ld t4, 224(sp)
  82         ld t5, 232(sp)
  83         ld t6, 240(sp)
  84 
  85         addi sp, sp, 256
  86 
  87         # return to whatever we were doing in the kernel.
  88         sret
  89 
  90         #
  91         # machine-mode timer interrupt.
  92         #
  93 .globl timervec
  94 .align 4
  95 timervec:
  96         # start.c has set up the memory that mscratch points to:
  97         # scratch[0,8,16] : register save area.
  98         # scratch[24] : address of CLINT's MTIMECMP register.
  99         # scratch[32] : desired interval between interrupts.
 100         
 101         csrrw a0, mscratch, a0
 102         sd a1, 0(a0)
 103         sd a2, 8(a0)
 104         sd a3, 16(a0)
 105 
 106         # schedule the next timer interrupt
 107         # by adding interval to mtimecmp.
 108         ld a1, 24(a0) # CLINT_MTIMECMP(hart)
 109         ld a2, 32(a0) # interval
 110         ld a3, 0(a1)
 111         add a3, a3, a2
 112         sd a3, 0(a1)
 113 
 114         # arrange for a supervisor software interrupt
 115         # after this handler returns.
 116         li a1, 2
 117         csrw sip, a1
 118 
 119         ld a3, 16(a0)
 120         ld a2, 8(a0)
 121         ld a1, 0(a0)
 122         csrrw a0, mscratch, a0
 123 
 124         mret